BX
BX Rm
arm_a32 ARM_A32 Branch branch indirect
A32_BX
Encoding
| encoding_kind | ARM_A32 |
| size_bits | 32 |
| variant | a32 |
| instr_word_bits | 32 |
| fixed_bits | E12FFF10 |
| fixed_mask | FFFFFFF0 |
| cond_field | [31:28] |
| set_flags | False |
Operands (1)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | Rm | REG | GPR | d (32b) | R | EXPLICIT | bits[3:0] |
Register effects
PC W (implicit)
Micro-ops sequence (1)
Ordered sequence of primitive operations the emulator dispatches. Ghidra-p-code-style — INTRINSIC escapes arch-specific ops that don't decompose cleanly.
- 0 BRANCHIND (Rm)