MUL
MUL Rd, Rm, Rs
arm_a32 ARM_A32 Multiply
A32_MUL
Encoding
| encoding_kind | ARM_A32 |
| size_bits | 32 |
| variant | a32 |
| instr_word_bits | 32 |
| fixed_bits | E0000090 |
| fixed_mask | FFF000F0 |
| cond_field | [31:28] |
| set_flags | False |
Operands (3)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | Rd | REG | GPR | d (32b) | W | EXPLICIT | bits[19:16] |
| 1 | Rm | REG | GPR | d (32b) | R | EXPLICIT | bits[3:0] |
| 2 | Rs | REG | GPR | d (32b) | R | EXPLICIT | bits[11:8] |
Micro-ops sequence (1)
Ordered sequence of primitive operations the emulator dispatches. Ghidra-p-code-style — INTRINSIC escapes arch-specific ops that don't decompose cleanly.
- 0 INT_MUL Rd ← (Rm, Rs) 32b