SUB

SUB Rd, Rn, #imm

arm_a32 ARM_A32 DataProc

A32_SUB_IMM

Encoding

encoding_kindARM_A32
size_bits32
varianta32
instr_word_bits32
fixed_bitsE2400000
fixed_maskFFF00000
cond_field[31:28]
set_flagsFalse

Operands (3)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 Rd REG GPR d (32b) RW EXPLICIT bits[15:12]
1 Rn REG GPR d (32b) R EXPLICIT bits[19:16]
2 imm12 IMM w (12b) R EXPLICIT bits[11:0]

Micro-ops sequence (1)

Ordered sequence of primitive operations the emulator dispatches. Ghidra-p-code-style — INTRINSIC escapes arch-specific ops that don't decompose cleanly.

  1. 0 INT_SUB Rd ← (Rn, imm12) 32b