SVC

SVC #imm24

arm_a32 ARM_A32 System call side_effects

A32_SVC

Encoding

encoding_kindARM_A32
size_bits32
varianta32
instr_word_bits32
fixed_bitsEF000000
fixed_maskFF000000
cond_field[31:28]
set_flagsFalse

Operands (1)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 imm24 IMM d (24b) R EXPLICIT bits[23:0]

Micro-ops sequence (1)

Ordered sequence of primitive operations the emulator dispatches. Ghidra-p-code-style — INTRINSIC escapes arch-specific ops that don't decompose cleanly.

  1. 0 INTRINSIC arm_supervisor_call (imm24)