MOV
MOV Rd, #imm8
arm_t16 ARM_T16 Thumb
T16_MOV_IMM8
Encoding
| encoding_kind | ARM_T16 |
| size_bits | 16 |
| variant | t16 |
| instr_word_bits | 16 |
| fixed_bits | 00002000 |
| fixed_mask | 0000F800 |
| set_flags | True |
Operands (2)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | Rd | REG | GPR | d (32b) | W | EXPLICIT | bits[10:8] |
| 1 | imm8 | IMM | b (8b) | R | EXPLICIT | bits[7:0] |
Flag effects (4)
N = WRITE
Z = WRITE
C = WRITE
V = WRITE
Context dependencies
SLEIGH-style: this encoding only matches when these context variables hold the required values.
T = 1
Micro-ops sequence (1)
Ordered sequence of primitive operations the emulator dispatches. Ghidra-p-code-style — INTRINSIC escapes arch-specific ops that don't decompose cleanly.
- 0 COPY Rd ← (Rd, imm8) 32b