STR
STR Rd, [Rn, #imm5]
arm_t16 ARM_T16 Thumb may_store
T16_STR_IMM5
Encoding
| encoding_kind | ARM_T16 |
| size_bits | 16 |
| variant | t16 |
| instr_word_bits | 16 |
| fixed_bits | 00006000 |
| fixed_mask | 0000F800 |
| set_flags | False |
Operands (3)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | Rd | REG | GPR | d (32b) | R | EXPLICIT | bits[2:0] |
| 1 | Rn | REG | GPR | d (32b) | R | EXPLICIT | bits[5:3] |
| 2 | imm5 | IMM | b (5b) | R | EXPLICIT | bits[10:6] |
Context dependencies
SLEIGH-style: this encoding only matches when these context variables hold the required values.
T = 1
Micro-ops sequence (2)
Ordered sequence of primitive operations the emulator dispatches. Ghidra-p-code-style — INTRINSIC escapes arch-specific ops that don't decompose cleanly.
- 0 INT_ADD addr ← (Rn, imm5) 32b
- 1 STORE (addr, Rd) 32b