ANDN

REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q MEM0:r:q REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q

x86_64 X86_LEGACY BMI1 BMI1 source: xed

XED_ANDN_X86_LEGACY_ONEBYTE_00_882004

Encoding

encoding_kindX86_LEGACY
opcode_bytes00
opcode_mapONEBYTE
mandatory_prefixF2
has_modrmTrue
vex_l0
requires_modelong
cpl3
raw_encodingVV1 0xF2 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0xF2 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]

Operands (18)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 REG0 REG w W EXPLICIT MODRM_REG
1 REG1 REG d R EXPLICIT MODRM_REG
2 MEM0 MEM d R EXPLICIT MODRM_RM
3 REG2 REG w W EXPLICIT MODRM_REG
4 REG3 REG d R EXPLICIT MODRM_REG
5 MEM1 MEM d R EXPLICIT MODRM_RM
6 REG4 REG w W EXPLICIT MODRM_REG
7 REG5 REG d R EXPLICIT MODRM_REG
8 REG6 REG d R EXPLICIT MODRM_REG
9 REG7 REG w W EXPLICIT MODRM_REG
10 REG8 REG d R EXPLICIT MODRM_REG
11 REG9 REG d R EXPLICIT MODRM_REG
12 REG10 REG w W EXPLICIT MODRM_REG
13 REG11 REG q R EXPLICIT MODRM_REG
14 MEM2 MEM q R EXPLICIT MODRM_RM
15 REG12 REG w W EXPLICIT MODRM_REG
16 REG13 REG q R EXPLICIT MODRM_REG
17 REG14 REG q R EXPLICIT MODRM_REG

Flag effects (6)

CF = SET_0 PF = UNDEFINED AF = UNDEFINED ZF = WRITE SF = WRITE OF = SET_0

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.