BEXTR_XOP
REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:d REG0=VGPRy_R():w:y MEM0:r:y IMM0:r:d REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:d REG0=VGPRy_R():w:y REG1=VGPRy_B():r:y IMM0:r:d
x86_64 X86_LEGACY TBM TBM source: xed
XED_BEXTR_XOP_X86_LEGACY_ONEBYTE_10_516685
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 10 10 10 10 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| vex_l | 0 |
| requires_mode | long |
| attributes | AMDONLY |
| cpl | 3 |
| raw_encoding | XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32() XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32() XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32() XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32() |
Operands (12)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | w | W | EXPLICIT | MODRM_REG | |
| 1 | MEM0 | MEM | d | R | EXPLICIT | MODRM_RM | |
| 2 | IMM0 | IMM | d | R | EXPLICIT | IMM | |
| 3 | REG1 | REG | w | W | EXPLICIT | MODRM_REG | |
| 4 | MEM1 | MEM | y | R | EXPLICIT | MODRM_RM | |
| 5 | IMM1 | IMM | d | R | EXPLICIT | IMM | |
| 6 | REG2 | REG | w | W | EXPLICIT | MODRM_REG | |
| 7 | REG3 | REG | d | R | EXPLICIT | MODRM_REG | |
| 8 | IMM2 | IMM | d | R | EXPLICIT | IMM | |
| 9 | REG4 | REG | w | W | EXPLICIT | MODRM_REG | |
| 10 | REG5 | REG | y | R | EXPLICIT | MODRM_REG | |
| 11 | IMM3 | IMM | d | R | EXPLICIT | IMM |
Flag effects (6)
CF = SET_0
PF = UNDEFINED
AF = UNDEFINED
ZF = WRITE
SF = UNDEFINED
OF = SET_0
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.