BLCI

REG0=VGPR32_N():w:d MEM0:r:d REG0=VGPRy_N():w:y MEM0:r:y REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y

x86_64 X86_LEGACY TBM TBM source: xed

XED_BLCI_X86_LEGACY_ONEBYTE_02_51860

Encoding

encoding_kindX86_LEGACY
opcode_bytes02 02 02 02
opcode_mapONEBYTE
mandatory_prefix-
has_modrmTrue
modrm.reg = /6/6
vex_l0
requires_modelong
attributesAMDONLY
cpl3
raw_encodingXOPV 0x02 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]

Operands (8)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 REG0 REG w W EXPLICIT MODRM_REG
1 MEM0 MEM d R EXPLICIT MODRM_RM
2 REG1 REG w W EXPLICIT MODRM_REG
3 MEM1 MEM y R EXPLICIT MODRM_RM
4 REG2 REG w W EXPLICIT MODRM_REG
5 REG3 REG d R EXPLICIT MODRM_REG
6 REG4 REG w W EXPLICIT MODRM_REG
7 REG5 REG y R EXPLICIT MODRM_REG

Flag effects (6)

CF = WRITE PF = UNDEFINED AF = UNDEFINED ZF = WRITE SF = WRITE OF = SET_0

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.