BLSI
REG0=VGPR32_N():w:d MEM0:r:d REG0=VGPR32_N():w:d MEM0:r:d REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d REG0=VGPR64_N():w:q MEM0:r:q REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q
x86_64 X86_LEGACY BMI1 BMI1 source: xed
XED_BLSI_X86_LEGACY_ONEBYTE_00_194554
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 00 |
| opcode_map | ONEBYTE |
| mandatory_prefix | F3 |
| has_modrm | True |
| modrm.reg = /3 | /3 |
| vex_l | 0 |
| requires_mode | long |
| cpl | 3 |
| raw_encoding | VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn] VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn] VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b011] RM[nnn] |
Operands (12)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | w | W | EXPLICIT | MODRM_REG | |
| 1 | MEM0 | MEM | d | R | EXPLICIT | MODRM_RM | |
| 2 | REG1 | REG | w | W | EXPLICIT | MODRM_REG | |
| 3 | MEM1 | MEM | d | R | EXPLICIT | MODRM_RM | |
| 4 | REG2 | REG | w | W | EXPLICIT | MODRM_REG | |
| 5 | REG3 | REG | d | R | EXPLICIT | MODRM_REG | |
| 6 | REG4 | REG | w | W | EXPLICIT | MODRM_REG | |
| 7 | REG5 | REG | d | R | EXPLICIT | MODRM_REG | |
| 8 | REG6 | REG | w | W | EXPLICIT | MODRM_REG | |
| 9 | MEM2 | MEM | q | R | EXPLICIT | MODRM_RM | |
| 10 | REG7 | REG | w | W | EXPLICIT | MODRM_REG | |
| 11 | REG8 | REG | q | R | EXPLICIT | MODRM_REG |
Flag effects (6)
CF = SET_0
PF = UNDEFINED
AF = UNDEFINED
ZF = WRITE
SF = WRITE
OF = SET_0
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.