CCMPNBE
APX APX_F_N3 x86_64
CCMPNBE is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category APX. This page lists its 12 encoding forms, distinguished by opcode bytes: 38, 39, 3A, 3B, 80, 81, 83.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_CCMPNBE_GPR8i8_GPR8i8_DFV_APX_N3
REG0=GPR8_B():r:b:i8 REG1=GPR8_R():r:b:i8
XED_CCMPNBE_GPR8i8_IMM8_DFV_APX_N3
REG0=GPR8_B():r:b:i8 IMM0:r:b:i8
XED_CCMPNBE_GPR8i8_MEMi8_DFV_APX_N3
REG0=GPR8_R():r:b:i8 MEM0:r:b:i8
XED_CCMPNBE_GPRv_GPRv_DFV_APX_N3
REG0=GPRv_B():r:v REG1=GPRv_R():r:v
XED_CCMPNBE_GPRv_IMM8_DFV_APX_N3
REG0=GPRv_B():r:v IMM0:r:b:i8
XED_CCMPNBE_GPRv_IMMz_DFV_APX_N3
REG0=GPRv_B():r:v IMM0:r:z
XED_CCMPNBE_GPRv_MEMv_DFV_APX_N3
REG0=GPRv_R():r:v MEM0:r:v
XED_CCMPNBE_MEMi8_GPR8i8_DFV_APX_N3
MEM0:r:b:i8 REG0=GPR8_R():r:b:i8
XED_CCMPNBE_MEMi8_IMM8_DFV_APX_N3
MEM0:r:b:i8 IMM0:r:b:i8
XED_CCMPNBE_MEMv_GPRv_DFV_APX_N3
MEM0:r:v REG0=GPRv_R():r:v
XED_CCMPNBE_MEMv_IMM8_DFV_APX_N3
MEM0:r:v IMM0:r:b:i8
XED_CCMPNBE_MEMv_IMMz_DFV_APX_N3
MEM0:r:v IMM0:r:z