CVTTSS2SI

REG0=GPR32_R():w:d:i32 MEM0:r:ss:f32 REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:ss:f32 REG0=GPR64_R():w:q:i64 MEM0:r:ss:f32 REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:ss:f32

x86_64 X86_LEGACY CONVERT SSE source: xed

XED_CVTTSS2SI_X86_LEGACY_0F_2C_680947

Encoding

encoding_kindX86_LEGACY
opcode_bytes2C 0F 2C 0F 2C 0F 2C
opcode_map0F
mandatory_prefix-
has_modrmTrue
rex_w1
attributessimd_scalar MXCSR
exception_classSSE_TYPE_3
cpl3
raw_encoding0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() 0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix 0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() 0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix

Operands (8)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 REG0 REG w W EXPLICIT MODRM_REG
1 MEM0 MEM f32 R EXPLICIT MODRM_RM
2 REG1 REG w W EXPLICIT MODRM_REG
3 REG2 REG f32 R EXPLICIT MODRM_REG
4 REG3 REG w W EXPLICIT MODRM_REG
5 MEM1 MEM f32 R EXPLICIT MODRM_RM
6 REG4 REG w W EXPLICIT MODRM_REG
7 REG5 REG f32 R EXPLICIT MODRM_REG

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.