DIV
BINARY APX_F x86_64
DIV is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category BINARY. This page lists its 10 encoding forms, distinguished by opcode bytes: F6, F7.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_DIV_GPR8i8_APX
REG0=GPR8_B():r:b:i8 REG1=XED_REG_AX:rw:SUPP
XED_DIV_GPR8i8_APX_N3
REG0=GPR8_B():r:b:i8 REG1=XED_REG_AX:rw:SUPP
XED_DIV_GPRv_APX
REG0=GPRv_B():r:v REG1=OrAX():rw:SUPP REG2=OrDX():rw:SUPP
XED_DIV_GPRv_APX_N3
REG0=GPRv_B():r:v REG1=OrAX():rw:SUPP REG2=OrDX():rw:SUPP
XED_DIV_MEMi8_APX
MEM0:r:b:i8 REG0=XED_REG_AX:rw:SUPP
XED_DIV_MEMi8_APX_N3
MEM0:r:b:i8 REG0=XED_REG_AX:rw:SUPP
XED_DIV_MEMv_APX
MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():rw:SUPP
XED_DIV_MEMv_APX_N3
MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():rw:SUPP
XED_DIV_X86_LEGACY_ONEBYTE_F6_544523
MEM0:r:b REG0=XED_REG_AX:rw:SUPP REG0=GPR8_B():r REG1=XED_REG_AX:rw:SUPP
XED_DIV_X86_LEGACY_ONEBYTE_F7_442141
MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():rw:SUPP REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():rw:SUPP