DIVSD
REG0=XMM_R():rw:sd MEM0:r:sd REG0=XMM_R():rw:sd REG1=XMM_B():r:sd
x86_64 X86_LEGACY SSE SSE2 source: xed
XED_DIVSD_X86_LEGACY_0F_5E_362005
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 5E 0F 5E |
| opcode_map | 0F |
| mandatory_prefix | - |
| has_modrm | True |
| attributes | simd_scalar MXCSR |
| exception_class | SSE_TYPE_3 |
| cpl | 3 |
| raw_encoding | 0x0F 0x5E f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 0x0F 0x5E f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() |
Operands (4)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | RW | EXPLICIT | MODRM_REG | ||
| 1 | MEM0 | MEM | R | EXPLICIT | MODRM_RM | ||
| 2 | REG1 | REG | RW | EXPLICIT | MODRM_REG | ||
| 3 | REG2 | REG | R | EXPLICIT | MODRM_REG |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.