ENCLU
REG0=XED_REG_EAX:r:SUPP \ REG1=XED_REG_RBX:crw:SUPP \ REG2=XED_REG_RCX:crw:SUPP \ REG3=XED_REG_RDX:crw:SUPP
x86_64 X86_LEGACY SGX SGX source: xed
XED_ENCLU_X86_LEGACY_0F_01_939135
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 01 |
| opcode_map | 0F |
| mandatory_prefix | - |
| has_modrm | True |
| modrm.reg = /2 | /2 |
| cpl | 3 |
| raw_encoding | 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix |
Operands (7)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | (=EAX) | R | SUPPRESSED | MODRM_REG | |
| 1 | \ | REG | R | EXPLICIT | |||
| 2 | REG1 | REG | (=RBX) | R | SUPPRESSED | MODRM_REG | |
| 3 | \ | REG | R | EXPLICIT | |||
| 4 | REG2 | REG | (=RCX) | R | SUPPRESSED | MODRM_REG | |
| 5 | \ | REG | R | EXPLICIT | |||
| 6 | REG3 | REG | (=RDX) | R | SUPPRESSED | MODRM_REG |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.