ENCLV
REG0=XED_REG_EAX:r:SUPP:d:u32 REG1=XED_REG_RBX:crw:SUPP:q:u64 REG2=XED_REG_RCX:crw:SUPP:q:u64 REG3=XED_REG_RDX:crw:SUPP:q:u64
x86_64 X86_LEGACY SGX SGX_ENCLV source: xed
XED_ENCLV
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 01 |
| opcode_map | 0F |
| mandatory_prefix | - |
| has_modrm | True |
| modrm.reg = /0 | /0 |
| cpl | 3 |
| raw_encoding | 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b000] no_refining_prefix |
Operands (4)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | (=EAX) | d | R | SUPPRESSED | MODRM_REG |
| 1 | REG1 | REG | (=RBX) | q | R | SUPPRESSED | MODRM_REG |
| 2 | REG2 | REG | (=RCX) | q | R | SUPPRESSED | MODRM_REG |
| 3 | REG3 | REG | (=RDX) | q | R | SUPPRESSED | MODRM_REG |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.