IMUL
REG0=GPRv_R():w MEM0:r:v IMM0:r:b:i8 REG0=GPRv_R():w REG1=GPRv_B():r IMM0:r:b:i8
x86_64 X86_LEGACY BINARY I186 source: xed
XED_IMUL_X86_LEGACY_ONEBYTE_6B_494968
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 6B 6B |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| imm_size_bytes | 1 signed |
| cpl | 3 |
| raw_encoding | 0x6B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SIMM8() 0x6B MOD[0b11] MOD=3 REG[rrr] RM[nnn] SIMM8() |
Operands (6)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | w | W | EXPLICIT | MODRM_REG | |
| 1 | MEM0 | MEM | v | R | EXPLICIT | MODRM_RM | |
| 2 | IMM0 | IMM | b | R | EXPLICIT | IMM | |
| 3 | REG1 | REG | w | W | EXPLICIT | MODRM_REG | |
| 4 | REG2 | REG | R | EXPLICIT | MODRM_REG | ||
| 5 | IMM1 | IMM | b | R | EXPLICIT | IMM |
Flag effects (6)
CF = WRITE
PF = UNDEFINED
AF = UNDEFINED
ZF = UNDEFINED
SF = UNDEFINED
OF = WRITE
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.