INSD

MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP

x86_64 X86_LEGACY IOSTRINGOP I386 source: xed

XED_INSD_X86_LEGACY_ONEBYTE_6D_535596

Encoding

encoding_kindX86_LEGACY
opcode_bytes6D 6D 6D 6D
opcode_mapONEBYTE
mandatory_prefix-
has_modrmFalse
rex_w1
requires_modelong
attributesfixed_base0 NOTSX
cpl3
raw_encoding0x6D mode16 66_prefix norep 0x6D mode32 no66_prefix norep 0x6D mode64 norexw_prefix no66_prefix norep 0x6D mode64 rexw_prefix norep

Operands (16)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 MEM0 MEM w W SUPPRESSED MODRM_RM
1 BASE0 REG RW SUPPRESSED
2 SEG0 REG R SUPPRESSED
3 REG0 REG (=DX) R SUPPRESSED MODRM_REG
4 MEM1 MEM w W SUPPRESSED MODRM_RM
5 BASE0 REG RW SUPPRESSED
6 SEG0 REG R SUPPRESSED
7 REG1 REG (=DX) R SUPPRESSED MODRM_REG
8 MEM2 MEM w W SUPPRESSED MODRM_RM
9 BASE0 REG RW SUPPRESSED
10 SEG0 REG R SUPPRESSED
11 REG2 REG (=DX) R SUPPRESSED MODRM_REG
12 MEM3 MEM w W SUPPRESSED MODRM_RM
13 BASE0 REG RW SUPPRESSED
14 SEG0 REG R SUPPRESSED
15 REG3 REG (=DX) R SUPPRESSED MODRM_REG

Flag effects (1)

DF = READ

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.