INVPCID
REG0=GPR64_R():r MEM0:r:dq REG0=GPR32_R():r MEM0:r:dq
x86_64 X86_LEGACY MISC INVPCID source: xed
XED_INVPCID_X86_LEGACY_0F38_82_541593
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 82 0F 38 82 |
| opcode_map | 0F38 |
| mandatory_prefix | - |
| has_modrm | True |
| requires_mode | long |
| attributes | RING0 NOTSX |
| cpl | 0 |
| raw_encoding | 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH() |
Operands (4)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | R | EXPLICIT | MODRM_REG | ||
| 1 | MEM0 | MEM | R | EXPLICIT | MODRM_RM | ||
| 2 | REG1 | REG | R | EXPLICIT | MODRM_REG | ||
| 3 | MEM1 | MEM | R | EXPLICIT | MODRM_RM |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.