JP

COND_BR I86 x86_64

JP is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category COND_BR. This page lists its 5 encoding forms, distinguished by opcode bytes: 7A, 8A.

Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.

X86_JP_X86_LEGACY_0F_8A_280120
rel16
X86_LEGACY 8A
X86_JP_X86_LEGACY_ONEBYTE_7A_655597
rel8
X86_LEGACY 7A
XED_JP_X86_LEGACY_0F_8A_618437
RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
X86_LEGACY 8A I86
XED_JP_X86_LEGACY_0F_8A_730705
RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
X86_LEGACY 8A I86
XED_JP_X86_LEGACY_ONEBYTE_7A_450245
RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP
X86_LEGACY 7A 7A I86