KMOVQ
KMASK APX_F_KOPQ x86_64
KMOVQ is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category KMASK. This page lists its 10 encoding forms, distinguished by opcode bytes: 90, 91, 92, 93.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_KMOVQ_GPR64u64_MASKmskw_APX
REG0=GPR64_R():w:q:u64 REG1=MASK_B():r:mskw
XED_KMOVQ_GPR64u64_MASKmskw_AVX512
REG0=VGPR64_R():w:q:u64 REG1=MASK_B():r:mskw
XED_KMOVQ_MASKmskw_GPR64u64_APX
REG0=MASK_R():w:mskw REG1=GPR64_B():r:q:u64
XED_KMOVQ_MASKmskw_GPR64u64_AVX512
REG0=MASK_R():w:mskw REG1=VGPR64_B():r:q:u64
XED_KMOVQ_MASKmskw_MASKu64_APX
REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u64
XED_KMOVQ_MASKmskw_MASKu64_AVX512
REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u64
XED_KMOVQ_MASKmskw_MEMu64_APX
REG0=MASK_R():w:mskw MEM0:r:q:u64
XED_KMOVQ_MASKmskw_MEMu64_AVX512
REG0=MASK_R():w:mskw MEM0:r:q:u64
XED_KMOVQ_MEMu64_MASKmskw_APX
MEM0:w:q:u64 REG0=MASK_R():r:mskw
XED_KMOVQ_MEMu64_MASKmskw_AVX512
MEM0:w:q:u64 REG0=MASK_R():r:mskw