KMOVW
KMASK APX_F_KOPW x86_64
KMOVW is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category KMASK. This page lists its 10 encoding forms, distinguished by opcode bytes: 90, 91, 92, 93.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_KMOVW_GPR32u32_MASKmskw_APX
REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw
XED_KMOVW_GPR32u32_MASKmskw_AVX512
REG0=VGPR32_R():w:d:u32 REG1=MASK_B():r:mskw
XED_KMOVW_MASKmskw_GPR32u32_APX
REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32
XED_KMOVW_MASKmskw_GPR32u32_AVX512
REG0=MASK_R():w:mskw REG1=VGPR32_B():r:d:u32
XED_KMOVW_MASKmskw_MASKu16_APX
REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u16
XED_KMOVW_MASKmskw_MASKu16_AVX512
REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u16
XED_KMOVW_MASKmskw_MEMu16_APX
REG0=MASK_R():w:mskw MEM0:r:wrd:u16
XED_KMOVW_MASKmskw_MEMu16_AVX512
REG0=MASK_R():w:mskw MEM0:r:wrd:u16
XED_KMOVW_MEMu16_MASKmskw_APX
MEM0:w:wrd:u16 REG0=MASK_R():r:mskw
XED_KMOVW_MEMu16_MASKmskw_AVX512
MEM0:w:wrd:u16 REG0=MASK_R():r:mskw