LZCNT
LZCNT APX_F_LZCNT x86_64
LZCNT is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category LZCNT. This page lists its 6 encoding forms, distinguished by opcode bytes: 0F, BD, F5.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
X86_LZCNT_X86_LEGACY_0F_BD_721802
rv, rv/mv
XED_LZCNT_GPRv_GPRv_APX
REG0=GPRv_R():w:v REG1=GPRv_B():r:v
XED_LZCNT_GPRv_GPRv_APX_N3
REG0=GPRv_R():w:v REG1=GPRv_B():r:v
XED_LZCNT_GPRv_MEMv_APX
REG0=GPRv_R():w:v MEM0:r:v
XED_LZCNT_GPRv_MEMv_APX_N3
REG0=GPRv_R():w:v MEM0:r:v
XED_LZCNT_X86_LEGACY_0F_BD_123234
REG0=GPRv_R():w:v MEM0:r:v REG0=GPRv_R():w:v REG1=GPRv_B():r:v