MOVDQU

REG0=XMM_R():w:dq MEM0:r:dq REG0=XMM_R():w:dq REG1=XMM_B():r:dq MEM0:w:dq REG0=XMM_R():r:dq REG0=XMM_B():w:dq REG1=XMM_R():r:dq

x86_64 X86_LEGACY DATAXFER SSE2 source: xed

XED_MOVDQU_XMMdq_XMMdq_0F6F MOVDQU_XMMdq_XMMdq_0F7F

Encoding

encoding_kindX86_LEGACY
opcode_bytes6F 0F 6F 0F 7F 0F 7F
opcode_map0F
mandatory_prefix-
has_modrmTrue
exception_classSSE_TYPE_4M
cpl3
raw_encoding0x0F 0x6F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 0x0F 0x6F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() 0x0F 0x7F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() 0x0F 0x7F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()

Operands (8)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 REG0 REG w W EXPLICIT MODRM_REG
1 MEM0 MEM R EXPLICIT MODRM_RM
2 REG1 REG w W EXPLICIT MODRM_REG
3 REG2 REG R EXPLICIT MODRM_REG
4 MEM1 MEM w W EXPLICIT MODRM_RM
5 REG3 REG R EXPLICIT MODRM_REG
6 REG4 REG w W EXPLICIT MODRM_REG
7 REG5 REG R EXPLICIT MODRM_REG

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.