MOVQ
DATAXFER SSE2 x86_64
MOVQ is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category DATAXFER. This page lists its 13 encoding forms, distinguished by opcode bytes: 0F, 6E, 6F, 7E, 7F, D6.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
X86_MOVQ_X86_LEGACY_0F_6E_584066
xmm[63:0], r64[63:0]/m64
X86_MOVQ_X86_LEGACY_0F_6E_773
mm, r64/m64
X86_MOVQ_X86_LEGACY_0F_6F_242698
mm, mm/m64
X86_MOVQ_X86_LEGACY_0F_7E_357756
r64/m64, xmm[63:0]
X86_MOVQ_X86_LEGACY_0F_7E_495218
r64/m64, mm
X86_MOVQ_X86_LEGACY_0F_7E_637135
xmm[63:0], xmm[63:0]/m64
X86_MOVQ_X86_LEGACY_0F_7F_193591
mm/m64, mm
X86_MOVQ_X86_LEGACY_0F_D6_219601
xmm[63:0]/m64, xmm[63:0]
XED_MOVQ_MEMq_XMMq_0F7E MOVQ_XMMdq_MEMq_0F7E
MEM0:w:q REG0=XMM_R():r:q REG0=XMM_R():w:dq MEM0:r:q
XED_MOVQ_MEMq_XMMq_0FD6
MEM0:w:q REG0=XMM_R():r:q
XED_MOVQ_MMXq_MEMq_0F6E MOVQ_MEMq_MMXq_0F7E MOVQ_MMXq_MEMq_0F6F MOVQ_MMXq_MMXq_0F6F MOVQ_MEMq_MMXq_0F7F MOVQ_MMXq_MMXq_0F7F
REG0=MMX_R():w:q MEM0:r:q REG0=MMX_R():w:q REG1=GPR64_B():r MEM0:w:q REG0=MMX_R():r:q REG0=GPR64_B():w REG1=MMX_R():r:q REG0=MMX_R():w:q MEM0:r:q REG0=MMX_R():w:q REG1=MMX_B():r:q MEM0:w:q REG0=MMX_R():r:q REG0=MMX_B():w:q REG1=MMX_R():r:q
XED_MOVQ_XMMdq_MEMq_0F6E
REG0=XMM_R():w:dq MEM0:r:q
XED_MOVQ_XMMdq_XMMq_0FD6 MOVQ_XMMdq_XMMq_0F7E
REG0=XMM_R():w:dq REG1=GPR64_B():r REG0=GPR64_B():w REG1=XMM_R():r:q REG0=XMM_B():w:dq REG1=XMM_R():r:q REG0=XMM_R():w:dq REG1=XMM_B():r:q