MOVSW

MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:w BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:w BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:w BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP

x86_64 X86_LEGACY STRINGOP I86 source: xed

XED_MOVSW_X86_LEGACY_ONEBYTE_A5_476667

Encoding

encoding_kindX86_LEGACY
opcode_bytesA5 A5 A5
opcode_mapONEBYTE
mandatory_prefix-
has_modrmFalse
requires_modelong
attributesfixed_base0 fixed_base1
cpl3
raw_encoding0xA5 mode16 no66_prefix norep OVERRIDE_SEG1() 0xA5 mode32 66_prefix norep OVERRIDE_SEG1() 0xA5 mode64 norexw_prefix 66_prefix norep norex2_prefix OVERRIDE_SEG1()

Operands (18)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 MEM0 MEM w W SUPPRESSED MODRM_RM
1 BASE0 REG RW SUPPRESSED
2 SEG0 REG R SUPPRESSED
3 MEM1 MEM w R SUPPRESSED MODRM_RM
4 BASE1 REG RW SUPPRESSED
5 SEG1 REG R SUPPRESSED
6 MEM2 MEM w W SUPPRESSED MODRM_RM
7 BASE0 REG RW SUPPRESSED
8 SEG0 REG R SUPPRESSED
9 MEM3 MEM w R SUPPRESSED MODRM_RM
10 BASE1 REG RW SUPPRESSED
11 SEG1 REG R SUPPRESSED
12 MEM4 MEM w W SUPPRESSED MODRM_RM
13 BASE0 REG RW SUPPRESSED
14 SEG0 REG R SUPPRESSED
15 MEM5 MEM w R SUPPRESSED MODRM_RM
16 BASE1 REG RW SUPPRESSED
17 SEG1 REG R SUPPRESSED

Flag effects (1)

DF = READ

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.