MPSADBW
REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8 IMM0:r:b REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8 IMM0:r:b
x86_64 X86_LEGACY SSE SSE4 source: xed
XED_MPSADBW_X86_LEGACY_0F3A_42_941598
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 42 0F 3A 42 |
| opcode_map | 0F3A |
| mandatory_prefix | - |
| has_modrm | True |
| imm_size_bytes | 1 |
| attributes | REQUIRES_ALIGNMENT DOUBLE_WIDE_OUTPUT |
| exception_class | SSE_TYPE_4 |
| cpl | 3 |
| raw_encoding | 0x0F 0x3A 0x42 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 0x0F 0x3A 0x42 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() |
Operands (6)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | RW | EXPLICIT | MODRM_REG | ||
| 1 | MEM0 | MEM | R | EXPLICIT | MODRM_RM | ||
| 2 | IMM0 | IMM | b | R | EXPLICIT | IMM | |
| 3 | REG1 | REG | RW | EXPLICIT | MODRM_REG | ||
| 4 | REG2 | REG | R | EXPLICIT | MODRM_REG | ||
| 5 | IMM1 | IMM | b | R | EXPLICIT | IMM |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.