MULX

REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d REG2=VGPR32_B():r:d REG3=XED_REG_EDX:r:SUPP REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d REG2=VGPR32_B():r:d REG3=XED_REG_EDX:r:SUPP REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d MEM0:r:d REG2=XED_REG_EDX:r:SUPP REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d MEM0:r:d REG2=XED_REG_EDX:r:SUPP REG0=VGPR64_R():w:q REG1=VGPR64_N():w:q REG2=VGPR64_B():r:q REG3=XED_REG_RDX:r:SUPP REG0=VGPR64_R():w:q REG1=VGPR64_N():w:q MEM0:r:q REG2=XED_REG_RDX:r:SUPP

x86_64 X86_LEGACY BMI2 BMI2 source: xed

XED_MULX_X86_LEGACY_ONEBYTE_F6_282273

Encoding

encoding_kindX86_LEGACY
opcode_bytesF6 F6 F6 F6 F6 F6
opcode_mapONEBYTE
mandatory_prefix-
has_modrmTrue
vex_l0
requires_modelong
cpl3
raw_encodingVV1 0xF6 VF2 V0F38 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0xF6 VF2 V0F38 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()

Operands (24)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 REG0 REG w W EXPLICIT MODRM_REG
1 REG1 REG w W EXPLICIT MODRM_REG
2 REG2 REG d R EXPLICIT MODRM_REG
3 REG3 REG (=EDX) R SUPPRESSED MODRM_REG
4 REG4 REG w W EXPLICIT MODRM_REG
5 REG5 REG w W EXPLICIT MODRM_REG
6 REG6 REG d R EXPLICIT MODRM_REG
7 REG7 REG (=EDX) R SUPPRESSED MODRM_REG
8 REG8 REG w W EXPLICIT MODRM_REG
9 REG9 REG w W EXPLICIT MODRM_REG
10 MEM0 MEM d R EXPLICIT MODRM_RM
11 REG10 REG (=EDX) R SUPPRESSED MODRM_REG
12 REG11 REG w W EXPLICIT MODRM_REG
13 REG12 REG w W EXPLICIT MODRM_REG
14 MEM1 MEM d R EXPLICIT MODRM_RM
15 REG13 REG (=EDX) R SUPPRESSED MODRM_REG
16 REG14 REG w W EXPLICIT MODRM_REG
17 REG15 REG w W EXPLICIT MODRM_REG
18 REG16 REG q R EXPLICIT MODRM_REG
19 REG17 REG (=RDX) R SUPPRESSED MODRM_REG
20 REG18 REG w W EXPLICIT MODRM_REG
21 REG19 REG w W EXPLICIT MODRM_REG
22 MEM2 MEM q R EXPLICIT MODRM_RM
23 REG20 REG (=RDX) R SUPPRESSED MODRM_REG

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.