MULX
REG0=GPR64_R():w:q:i64 REG1=GPR64_N():w:q:i64 MEM0:r:q:i64 REG2=XED_REG_RDX:r:SUPP:q:i64
x86_64 X86_LEGACY BMI2 APX_F_BMI2 source: xed
XED_MULX_GPR64i64_GPR64i64_MEMi64_APX
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | F6 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| vex_l | 0 |
| requires_mode | long |
| attributes | DISP8_NO_SCALE |
| exception_class | APX-EVEX-BMI |
| cpl | 3 |
| raw_encoding | EVV 0xF6 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() ND=0 NF=0 W1 VL128 mode64 ZEROING=0 EVAPX() |
Operands (4)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | w | W | EXPLICIT | MODRM_REG | |
| 1 | REG1 | REG | w | W | EXPLICIT | MODRM_REG | |
| 2 | MEM0 | MEM | q | R | EXPLICIT | MODRM_RM | |
| 3 | REG2 | REG | (=RDX) | q | R | SUPPRESSED | MODRM_REG |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.