PADDQ
MMX SSE2MMX x86_64
PADDQ is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category MMX. This page lists its 4 encoding forms, distinguished by opcode bytes: 0F, D4.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
X86_PADDQ_X86_LEGACY_0F_D4_242698
mm, mm/m64
X86_PADDQ_X86_LEGACY_0F_D4_898451
xmm, xmm/m128
XED_PADDQ_X86_LEGACY_0F_D4_208874
REG0=XMM_R():rw:dq MEM0:r:dq REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
XED_PADDQ_X86_LEGACY_0F_D4_481152
REG0=MMX_R():rw:q:u64 MEM0:r:q:u64 REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q:u64