PALIGNR
MMX SSSE3MMX x86_64
PALIGNR is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category MMX. This page lists its 4 encoding forms, distinguished by opcode bytes: 0F, 3A.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
X86_PALIGNR_X86_LEGACY_0F3A_0F_147292
xmm, xmm/m128, imm8
X86_PALIGNR_X86_LEGACY_0F3A_0F_672992
mm, mm/m64, imm8
XED_PALIGNR_X86_LEGACY_0F_0F_331519
REG0=MMX_R():rw:q MEM0:r:q IMM0:r:b REG0=MMX_R():rw:q REG1=MMX_B():r:q IMM0:r:b
XED_PALIGNR_X86_LEGACY_0F_0F_664117
REG0=XMM_R():rw:dq MEM0:r:dq IMM0:r:b REG0=XMM_R():rw:dq REG1=XMM_B():r:dq IMM0:r:b