PEXTRQ
MEM0:w:q REG0=XMM_R():r:dq IMM0:r:b REG0=GPR64_B():w:q REG1=XMM_R():r:dq IMM0:r:b
x86_64 X86_LEGACY SSE SSE4 source: xed
XED_PEXTRQ_X86_LEGACY_0F3A_16_796935
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 16 0F 3A 16 |
| opcode_map | 0F3A |
| mandatory_prefix | - |
| has_modrm | True |
| rex_w | 1 |
| imm_size_bytes | 1 |
| requires_mode | long |
| exception_class | SSE_TYPE_5 |
| cpl | 3 |
| raw_encoding | 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() |
Operands (6)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | MEM0 | MEM | w | W | EXPLICIT | MODRM_RM | |
| 1 | REG0 | REG | R | EXPLICIT | MODRM_REG | ||
| 2 | IMM0 | IMM | b | R | EXPLICIT | IMM | |
| 3 | REG1 | REG | w | W | EXPLICIT | MODRM_REG | |
| 4 | REG2 | REG | R | EXPLICIT | MODRM_REG | ||
| 5 | IMM1 | IMM | b | R | EXPLICIT | IMM |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.