PHSUBD
MMX SSSE3MMX x86_64
PHSUBD is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category MMX. This page lists its 4 encoding forms, distinguished by opcode bytes: 06, 0F, 38.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
X86_PHSUBD_X86_LEGACY_0F38_06_242698
mm, mm/m64
X86_PHSUBD_X86_LEGACY_0F38_06_898451
xmm, xmm/m128
XED_PHSUBD_X86_LEGACY_0F38_06_264210
REG0=MMX_R():rw:q MEM0:r:q REG0=MMX_R():rw:q REG1=MMX_B():r:q
XED_PHSUBD_X86_LEGACY_0F38_06_803263
REG0=XMM_R():rw:dq MEM0:r:dq REG0=XMM_R():rw:dq REG1=XMM_B():r:dq