POP
POP I86 x86_64
POP is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category POP. This page lists its 11 encoding forms, distinguished by opcode bytes: 00, 07, 17, 1F, 8F, A1, A9.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
X86_POP_X86_LEGACY_ONEBYTE_00_419659
r16
X86_POP_X86_LEGACY_ONEBYTE_8F_3897
r32/m32
X86_POP_X86_LEGACY_ONEBYTE_8F_812183
r64/m64
X86_POP_X86_LEGACY_ONEBYTE_8F_866660
r16/m16
XED_POP_GPRv_58 POP_GPRv_58
REG0=GPRv_SB():w REG1=XED_REG_STACKPOP:rw:spw:SUPP REG0=GPRv_SB():w REG1=XED_REG_STACKPOP:rw:spw:SUPP
XED_POP_GPRv_8F
MEM0:w:v REG0=XED_REG_STACKPOP:rw:spw:SUPP REG0=GPRv_B():w REG1=XED_REG_STACKPOP:rw:spw:SUPP
XED_POP_X86_LEGACY_0F_A1_972701
REG0=XED_REG_FS:w:IMPL REG1=XED_REG_STACKPOP:rw:spw:SUPP
XED_POP_X86_LEGACY_0F_A9_743888
REG0=XED_REG_GS:w:IMPL REG1=XED_REG_STACKPOP:rw:spw:SUPP
XED_POP_X86_LEGACY_ONEBYTE_07_531876
REG0=XED_REG_ES:w:IMPL REG1=XED_REG_STACKPOP:rw:spw:SUPP
XED_POP_X86_LEGACY_ONEBYTE_17_981528
REG0=XED_REG_SS:w:IMPL REG1=XED_REG_STACKPOP:rw:spw:SUPP
XED_POP_X86_LEGACY_ONEBYTE_1F_739815
REG0=XED_REG_DS:w:IMPL REG1=XED_REG_STACKPOP:rw:spw:SUPP