PSLLD
MMX PENTIUMMMX x86_64
PSLLD is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category MMX. This page lists its 7 encoding forms, distinguished by opcode bytes: 0F, 72, F2.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
X86_PSLLD_X86_LEGACY_0F_72_771567
xmm, imm8
X86_PSLLD_X86_LEGACY_0F_F2_898451
xmm, xmm/m128
XED_PSLLD_X86_LEGACY_0F_72_341659
REG0=MMX_B():rw:q:u32 IMM0:r:b
XED_PSLLD_X86_LEGACY_0F_72_841617
REG0=XMM_B():rw:dq:u32 IMM0:r:b
XED_PSLLD_X86_LEGACY_0F_F2_112356
REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
XED_PSLLD_X86_LEGACY_0F_F2_606375
REG0=XMM_R():rw:dq MEM0:r:dq
XED_PSLLD_X86_LEGACY_0F_F2_653399
REG0=MMX_R():rw:q:u32 MEM0:r:q REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q