PSLLW
MMX PENTIUMMMX x86_64
PSLLW is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category MMX. This page lists its 7 encoding forms, distinguished by opcode bytes: 0F, 71, F1.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
X86_PSLLW_X86_LEGACY_0F_71_771567
xmm, imm8
X86_PSLLW_X86_LEGACY_0F_F1_898451
xmm, xmm/m128
XED_PSLLW_X86_LEGACY_0F_71_310547
REG0=XMM_B():rw:dq:u16 IMM0:r:b
XED_PSLLW_X86_LEGACY_0F_71_324191
REG0=MMX_B():rw:q:u16 IMM0:r:b
XED_PSLLW_X86_LEGACY_0F_F1_144723
REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq
XED_PSLLW_X86_LEGACY_0F_F1_309096
REG0=MMX_R():rw:q:u16 MEM0:r:q REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q
XED_PSLLW_X86_LEGACY_0F_F1_331588
REG0=XMM_R():rw:dq:u16 MEM0:r:dq