PSRLW
MMX PENTIUMMMX x86_64
PSRLW is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category MMX. This page lists its 8 encoding forms, distinguished by opcode bytes: 71, D1.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
X86_PSRLW_X86_LEGACY_0F_71_771567
xmm, imm8
X86_PSRLW_X86_LEGACY_0F_D1_898451
xmm, xmm/m128
XED_PSRLW_X86_LEGACY_0F_71_770764
REG0=XMM_B():rw:dq:u16 IMM0:r:b
XED_PSRLW_X86_LEGACY_0F_71_855008
REG0=MMX_B():rw:q:u16 IMM0:r:b
XED_PSRLW_X86_LEGACY_0F_D1_187817
REG0=XMM_R():rw:dq REG1=XMM_B():r:dq
XED_PSRLW_X86_LEGACY_0F_D1_389962
REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q
XED_PSRLW_X86_LEGACY_0F_D1_784273
REG0=MMX_R():rw:q:u16 MEM0:r:q
XED_PSRLW_X86_LEGACY_0F_D1_844298
REG0=XMM_R():rw:dq MEM0:r:dq