PUSH

PUSH I86 x86_64

PUSH is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category PUSH. This page lists its 15 encoding forms, distinguished by opcode bytes: 00, 06, 0E, 16, 1E, 68, 6A, A0 and 2 more.

Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.

X86_PUSH_X86_LEGACY_ONEBYTE_00_419659

X86_PUSH_X86_LEGACY_ONEBYTE_68_747422

X86_PUSH_X86_LEGACY_ONEBYTE_FF_3897

X86_LEGACY FF /6

X86_PUSH_X86_LEGACY_ONEBYTE_FF_812183

X86_LEGACY FF /6

X86_PUSH_X86_LEGACY_ONEBYTE_FF_866660

X86_LEGACY FF /6

XED_PUSH_GPRv_50 PUSH_GPRv_50

REG0=GPRv_SB():r REG1=XED_REG_STACKPUSH:rw:spw:SUPP REG0=GPRv_SB():r REG1=XED_REG_STACKPUSH:rw:spw:SUPP

X86_LEGACY 00 I86

XED_PUSH_GPRv_FFr6

MEM0:r:v REG0=XED_REG_STACKPUSH:rw:spw:SUPP REG0=GPRv_B():r REG1=XED_REG_STACKPUSH:rw:spw:SUPP

X86_LEGACY FF FF /6 I86

XED_PUSH_X86_LEGACY_0F_A0_387071

REG0=XED_REG_FS:r:IMPL REG1=XED_REG_STACKPUSH:rw:spw:SUPP

X86_LEGACY A0 I86

XED_PUSH_X86_LEGACY_0F_A8_526554

REG0=XED_REG_GS:r:IMPL REG1=XED_REG_STACKPUSH:rw:spw:SUPP

X86_LEGACY A8 I86

XED_PUSH_X86_LEGACY_ONEBYTE_06_556783

REG0=XED_REG_ES:r:IMPL REG1=XED_REG_STACKPUSH:rw:spw:SUPP

X86_LEGACY 06 I86

XED_PUSH_X86_LEGACY_ONEBYTE_0E_629728

REG0=XED_REG_CS:r:IMPL REG1=XED_REG_STACKPUSH:rw:spw:SUPP

X86_LEGACY 0E I86

XED_PUSH_X86_LEGACY_ONEBYTE_16_143289

REG0=XED_REG_SS:r:IMPL REG1=XED_REG_STACKPUSH:rw:spw:SUPP

X86_LEGACY 16 I86

XED_PUSH_X86_LEGACY_ONEBYTE_1E_317352

REG0=XED_REG_DS:r:IMPL REG1=XED_REG_STACKPUSH:rw:spw:SUPP

X86_LEGACY 1E I86

XED_PUSH_X86_LEGACY_ONEBYTE_68_499837

IMM0:r:z REG0=XED_REG_STACKPUSH:rw:spw:SUPP

X86_LEGACY 68 I186

XED_PUSH_X86_LEGACY_ONEBYTE_6A_349709

IMM0:r:b:i8 REG0=XED_REG_STACKPUSH:rw:spw:SUPP

X86_LEGACY 6A I186