RCR
ROTATE APX_F x86_64
RCR is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category ROTATE. This page lists its 31 encoding forms, distinguished by opcode bytes: C0, C1, D0, D1, D2, D3.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_RCR_GPR8i8_CL_APX
REG0=GPR8_B():rw:b:i8 REG1=XED_REG_CL:r:IMPL
XED_RCR_GPR8i8_GPR8i8_CL_APX_N3
REG0=GPR8_N():w:b:i8 REG1=GPR8_B():r:b:i8 REG2=XED_REG_CL:r:IMPL
XED_RCR_GPR8i8_GPR8i8_IMM8_APX_N3
REG0=GPR8_N():w:b:i8 REG1=GPR8_B():r:b:i8 IMM0:r:b
XED_RCR_GPR8i8_GPR8i8_ONE_APX_N3
REG0=GPR8_N():w:b:i8 REG1=GPR8_B():r:b:i8 IMM0:r:IMPL:b
XED_RCR_GPR8i8_IMM8_APX
REG0=GPR8_B():rw:b:i8 IMM0:r:b
XED_RCR_GPR8i8_MEMi8_CL_APX_N3
REG0=GPR8_N():w:b:i8 MEM0:r:b:i8 REG1=XED_REG_CL:r:IMPL
XED_RCR_GPR8i8_MEMi8_IMM8_APX_N3
REG0=GPR8_N():w:b:i8 MEM0:r:b:i8 IMM0:r:b
XED_RCR_GPR8i8_MEMi8_ONE_APX_N3
REG0=GPR8_N():w:b:i8 MEM0:r:b:i8 IMM0:r:IMPL:b
XED_RCR_GPR8i8_ONE_APX
REG0=GPR8_B():rw:b:i8 IMM0:r:IMPL:b
XED_RCR_GPRv_CL_APX
REG0=GPRv_B():rw:v REG1=XED_REG_CL:r:IMPL
XED_RCR_GPRv_GPRv_CL_APX_N3
REG0=GPRv_N():w:v REG1=GPRv_B():r:v REG2=XED_REG_CL:r:IMPL
XED_RCR_GPRv_GPRv_IMM8_APX_N3
REG0=GPRv_N():w:v REG1=GPRv_B():r:v IMM0:r:b
XED_RCR_GPRv_GPRv_ONE_APX_N3
REG0=GPRv_N():w:v REG1=GPRv_B():r:v IMM0:r:IMPL:b
XED_RCR_GPRv_IMM8_APX
REG0=GPRv_B():rw:v IMM0:r:b
XED_RCR_GPRv_MEMv_CL_APX_N3
REG0=GPRv_N():w:v MEM0:r:v REG1=XED_REG_CL:r:IMPL
XED_RCR_GPRv_MEMv_IMM8_APX_N3
REG0=GPRv_N():w:v MEM0:r:v IMM0:r:b
XED_RCR_GPRv_MEMv_ONE_APX_N3
REG0=GPRv_N():w:v MEM0:r:v IMM0:r:IMPL:b
XED_RCR_GPRv_ONE_APX
REG0=GPRv_B():rw:v IMM0:r:IMPL:b
XED_RCR_MEMb_ONE RCR_GPR8_ONE
MEM0:rw:b IMM0:r:b:IMPL REG0=GPR8_B():rw IMM0:r:b:IMPL
XED_RCR_MEMi8_CL_APX
MEM0:rw:b:i8 REG0=XED_REG_CL:r:IMPL
XED_RCR_MEMi8_IMM8_APX
MEM0:rw:b:i8 IMM0:r:b
XED_RCR_MEMi8_ONE_APX
MEM0:rw:b:i8 IMM0:r:IMPL:b
XED_RCR_MEMv_CL_APX
MEM0:rw:v REG0=XED_REG_CL:r:IMPL
XED_RCR_MEMv_IMM8_APX
MEM0:rw:v IMM0:r:b
XED_RCR_MEMv_ONE_APX
MEM0:rw:v IMM0:r:IMPL:b
XED_RCR_MEMv_ONE RCR_GPRv_ONE
MEM0:rw:v IMM0:r:b:IMPL REG0=GPRv_B():rw IMM0:r:b:IMPL
XED_RCR_X86_LEGACY_ONEBYTE_C0_503676
MEM0:rw:b IMM0:r:b REG0=GPR8_B():rw IMM0:r:b
XED_RCR_X86_LEGACY_ONEBYTE_C1_219404
MEM0:rw:v IMM0:r:b REG0=GPRv_B():rw IMM0:r:b
XED_RCR_X86_LEGACY_ONEBYTE_D2_698948
MEM0:rw:b REG0=XED_REG_CL:r:IMPL REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL
XED_RCR_X86_LEGACY_ONEBYTE_D3_216190
REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL
XED_RCR_X86_LEGACY_ONEBYTE_D3_897899
MEM0:rw:v REG0=XED_REG_CL:r:IMPL