REP_MOVSW
MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP
x86_64 X86_LEGACY STRINGOP I86 source: xed
XED_REP_MOVSW_X86_LEGACY_ONEBYTE_A5_129708
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | A5 A5 A5 A5 A5 A5 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | False |
| requires_mode | long |
| attributes | REP fixed_base0 fixed_base1 |
| cpl | 3 |
| raw_encoding | 0xA5 mode16 no66_prefix repe OVERRIDE_SEG1() 0xA5 mode32 66_prefix repe OVERRIDE_SEG1() 0xA5 mode64 norexw_prefix 66_prefix norex2_prefix repe OVERRIDE_SEG1() 0xA5 mode16 no66_prefix repne OVERRIDE_SEG1() 0xA5 mode32 66_prefix repne OVERRIDE_SEG1() 0xA5 mode64 norexw_prefix 66_prefix repne norex2_prefix OVERRIDE_SEG1() |
Operands (42)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | MEM0 | MEM | w | CW | SUPPRESSED | MODRM_RM | |
| 1 | BASE0 | REG | R | SUPPRESSED | |||
| 2 | SEG0 | REG | R | SUPPRESSED | |||
| 3 | MEM1 | MEM | w | CR | SUPPRESSED | MODRM_RM | |
| 4 | BASE1 | REG | R | SUPPRESSED | |||
| 5 | SEG1 | REG | R | SUPPRESSED | |||
| 6 | REG0 | REG | R | SUPPRESSED | MODRM_REG | ||
| 7 | MEM2 | MEM | w | CW | SUPPRESSED | MODRM_RM | |
| 8 | BASE0 | REG | R | SUPPRESSED | |||
| 9 | SEG0 | REG | R | SUPPRESSED | |||
| 10 | MEM3 | MEM | w | CR | SUPPRESSED | MODRM_RM | |
| 11 | BASE1 | REG | R | SUPPRESSED | |||
| 12 | SEG1 | REG | R | SUPPRESSED | |||
| 13 | REG1 | REG | R | SUPPRESSED | MODRM_REG | ||
| 14 | MEM4 | MEM | w | CW | SUPPRESSED | MODRM_RM | |
| 15 | BASE0 | REG | R | SUPPRESSED | |||
| 16 | SEG0 | REG | R | SUPPRESSED | |||
| 17 | MEM5 | MEM | w | CR | SUPPRESSED | MODRM_RM | |
| 18 | BASE1 | REG | R | SUPPRESSED | |||
| 19 | SEG1 | REG | R | SUPPRESSED | |||
| 20 | REG2 | REG | R | SUPPRESSED | MODRM_REG | ||
| 21 | MEM6 | MEM | w | CW | SUPPRESSED | MODRM_RM | |
| 22 | BASE0 | REG | R | SUPPRESSED | |||
| 23 | SEG0 | REG | R | SUPPRESSED | |||
| 24 | MEM7 | MEM | w | CR | SUPPRESSED | MODRM_RM | |
| 25 | BASE1 | REG | R | SUPPRESSED | |||
| 26 | SEG1 | REG | R | SUPPRESSED | |||
| 27 | REG3 | REG | R | SUPPRESSED | MODRM_REG | ||
| 28 | MEM8 | MEM | w | CW | SUPPRESSED | MODRM_RM | |
| 29 | BASE0 | REG | R | SUPPRESSED | |||
| 30 | SEG0 | REG | R | SUPPRESSED | |||
| 31 | MEM9 | MEM | w | CR | SUPPRESSED | MODRM_RM | |
| 32 | BASE1 | REG | R | SUPPRESSED | |||
| 33 | SEG1 | REG | R | SUPPRESSED | |||
| 34 | REG4 | REG | R | SUPPRESSED | MODRM_REG | ||
| 35 | MEM10 | MEM | w | CW | SUPPRESSED | MODRM_RM | |
| 36 | BASE0 | REG | R | SUPPRESSED | |||
| 37 | SEG0 | REG | R | SUPPRESSED | |||
| 38 | MEM11 | MEM | w | CR | SUPPRESSED | MODRM_RM | |
| 39 | BASE1 | REG | R | SUPPRESSED | |||
| 40 | SEG1 | REG | R | SUPPRESSED | |||
| 41 | REG5 | REG | R | SUPPRESSED | MODRM_REG |
Flag effects (1)
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.