REP_OUTSD

REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP

x86_64 X86_LEGACY IOSTRINGOP I386 source: xed

XED_REP_OUTSD_X86_LEGACY_ONEBYTE_6F_102602

Encoding

encoding_kind	X86_LEGACY
opcode_bytes	6F 6F 6F 6F 6F 6F 6F 6F
opcode_map	ONEBYTE
mandatory_prefix	-
has_modrm	False
rex_w	1
requires_mode	long
attributes	REP fixed_base0 NOTSX
cpl	3
raw_encoding	0x6F mode16 66_prefix repe OVERRIDE_SEG0() 0x6F mode32 no66_prefix repe OVERRIDE_SEG0() 0x6F mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG0() 0x6F mode64 rexw_prefix repe OVERRIDE_SEG0() 0x6F mode16 66_prefix repne OVERRIDE_SEG0() 0x6F mode32 no66_prefix repne OVERRIDE_SEG0() 0x6F mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG0() 0x6F mode64 rexw_prefix repne OVERRIDE_SEG0()

Operands (40)

#	Role	Kind	Class / Reg	Width	Access	Visibility	Encoded in
0	REG0	REG	(=DX)		R	SUPPRESSED	MODRM_REG
1	MEM0	MEM		d	CR	SUPPRESSED	MODRM_RM
2	BASE0	REG			R	SUPPRESSED
3	SEG0	REG			R	SUPPRESSED
4	REG1	REG			R	SUPPRESSED	MODRM_REG
5	REG2	REG	(=DX)		R	SUPPRESSED	MODRM_REG
6	MEM1	MEM		d	CR	SUPPRESSED	MODRM_RM
7	BASE0	REG			R	SUPPRESSED
8	SEG0	REG			R	SUPPRESSED
9	REG3	REG			R	SUPPRESSED	MODRM_REG
10	REG4	REG	(=DX)		R	SUPPRESSED	MODRM_REG
11	MEM2	MEM		d	CR	SUPPRESSED	MODRM_RM
12	BASE0	REG			R	SUPPRESSED
13	SEG0	REG			R	SUPPRESSED
14	REG5	REG			R	SUPPRESSED	MODRM_REG
15	REG6	REG	(=DX)		R	SUPPRESSED	MODRM_REG
16	MEM3	MEM		d	CR	SUPPRESSED	MODRM_RM
17	BASE0	REG			R	SUPPRESSED
18	SEG0	REG			R	SUPPRESSED
19	REG7	REG			R	SUPPRESSED	MODRM_REG
20	REG8	REG	(=DX)		R	SUPPRESSED	MODRM_REG
21	MEM4	MEM		d	CR	SUPPRESSED	MODRM_RM
22	BASE0	REG			R	SUPPRESSED
23	SEG0	REG			R	SUPPRESSED
24	REG9	REG			R	SUPPRESSED	MODRM_REG
25	REG10	REG	(=DX)		R	SUPPRESSED	MODRM_REG
26	MEM5	MEM		d	CR	SUPPRESSED	MODRM_RM
27	BASE0	REG			R	SUPPRESSED
28	SEG0	REG			R	SUPPRESSED
29	REG11	REG			R	SUPPRESSED	MODRM_REG
30	REG12	REG	(=DX)		R	SUPPRESSED	MODRM_REG
31	MEM6	MEM		d	CR	SUPPRESSED	MODRM_RM
32	BASE0	REG			R	SUPPRESSED
33	SEG0	REG			R	SUPPRESSED
34	REG13	REG			R	SUPPRESSED	MODRM_REG
35	REG14	REG	(=DX)		R	SUPPRESSED	MODRM_REG
36	MEM7	MEM		d	CR	SUPPRESSED	MODRM_RM
37	BASE0	REG			R	SUPPRESSED
38	SEG0	REG			R	SUPPRESSED
39	REG15	REG			R	SUPPRESSED	MODRM_REG

Flag effects (1)

DF = READ

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.