RORX

REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:b REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:b REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:b REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:b REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q IMM0:r:b REG0=VGPR64_R():w:q MEM0:r:q IMM0:r:b

x86_64 X86_LEGACY BMI2 BMI2 source: xed

XED_RORX_X86_LEGACY_ONEBYTE_F0_931856

Encoding

encoding_kindX86_LEGACY
opcode_bytesF0 F0 F0 F0 F0 F0
opcode_mapONEBYTE
mandatory_prefix-
has_modrmTrue
vex_l0
imm_size_bytes1
requires_modelong
cpl3
raw_encodingVV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()

Operands (18)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 REG0 REG w W EXPLICIT MODRM_REG
1 REG1 REG d R EXPLICIT MODRM_REG
2 IMM0 IMM b R EXPLICIT IMM
3 REG2 REG w W EXPLICIT MODRM_REG
4 REG3 REG d R EXPLICIT MODRM_REG
5 IMM1 IMM b R EXPLICIT IMM
6 REG4 REG w W EXPLICIT MODRM_REG
7 MEM0 MEM d R EXPLICIT MODRM_RM
8 IMM2 IMM b R EXPLICIT IMM
9 REG5 REG w W EXPLICIT MODRM_REG
10 MEM1 MEM d R EXPLICIT MODRM_RM
11 IMM3 IMM b R EXPLICIT IMM
12 REG6 REG w W EXPLICIT MODRM_REG
13 REG7 REG q R EXPLICIT MODRM_REG
14 IMM4 IMM b R EXPLICIT IMM
15 REG8 REG w W EXPLICIT MODRM_REG
16 MEM2 MEM q R EXPLICIT MODRM_RM
17 IMM5 IMM b R EXPLICIT IMM

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.