SHL
MEM0:rw:v IMM0:r:b:IMPL MEM0:rw:v IMM0:r:b:IMPL REG0=GPRv_B():rw IMM0:r:b:IMPL
x86_64 X86_LEGACY SHIFT I86 source: xed
XED_SHL_MEMv_ONE_D1r6 SHL_MEMv_ONE_D1r4 SHL_GPRv_ONE_D1r4
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | D1 D1 D1 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| modrm.reg = /4 | /4 |
| attributes | IMPLICIT_ONE |
| cpl | 3 |
| raw_encoding | 0xD1 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() ONE() 0xD1 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() ONE() 0xD1 MOD[0b11] MOD=3 REG[0b100] RM[nnn] ONE() |
Operands (6)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | MEM0 | MEM | v | RW | EXPLICIT | MODRM_RM | |
| 1 | IMM0 | IMM | b | R | IMPLICIT | IMM | |
| 2 | MEM1 | MEM | v | RW | EXPLICIT | MODRM_RM | |
| 3 | IMM1 | IMM | b | R | IMPLICIT | IMM | |
| 4 | REG0 | REG | RW | EXPLICIT | MODRM_REG | ||
| 5 | IMM2 | IMM | b | R | IMPLICIT | IMM |
Flag effects (6)
CF = WRITE
PF = WRITE
AF = UNDEFINED
ZF = WRITE
SF = WRITE
OF = WRITE
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.