SHL
MEM0:rw:b REG0=XED_REG_CL:r:IMPL REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL
x86_64 X86_LEGACY SHIFT I86 source: xed
XED_SHL_MEMb_CL_D2r6 SHL_GPR8_CL_D2r6
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | D2 D2 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| modrm.reg = /6 | /6 |
| attributes | BYTEOP UNDOCUMENTED |
| cpl | 3 |
| raw_encoding | 0xD2 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() 0xD2 MOD[0b11] MOD=3 REG[0b110] RM[nnn] |
Operands (4)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | MEM0 | MEM | b | RW | EXPLICIT | MODRM_RM | |
| 1 | REG0 | REG | (=CL) | R | IMPLICIT | MODRM_REG | |
| 2 | REG1 | REG | RW | EXPLICIT | MODRM_REG | ||
| 3 | REG2 | REG | (=CL) | R | IMPLICIT | MODRM_REG |
Flag effects (6)
CF = WRITE
PF = WRITE
AF = UNDEFINED
ZF = WRITE
SF = WRITE
OF = UNDEFINED
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.