SHL
REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL
x86_64 X86_LEGACY SHIFT I86 source: xed
XED_SHL_GPRv_CL_D3r4
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | D3 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| modrm.reg = /4 | /4 |
| cpl | 3 |
| raw_encoding | 0xD3 MOD[0b11] MOD=3 REG[0b100] RM[nnn] |
Operands (2)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | RW | EXPLICIT | MODRM_REG | ||
| 1 | REG1 | REG | (=CL) | R | IMPLICIT | MODRM_REG |
Flag effects (6)
CF = WRITE
PF = WRITE
AF = UNDEFINED
ZF = WRITE
SF = WRITE
OF = UNDEFINED
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.