SHLX

REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q

x86_64 X86_LEGACY BMI2 BMI2 source: xed

XED_SHLX_X86_LEGACY_ONEBYTE_F7_742459

Encoding

encoding_kindX86_LEGACY
opcode_bytesF7 F7 F7 F7 F7 F7
opcode_mapONEBYTE
mandatory_prefix-
has_modrmTrue
vex_l0
requires_modelong
cpl3
raw_encodingVV1 0xF7 V0F38 V66 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0xF7 V0F38 V66 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]

Operands (18)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 REG0 REG w W EXPLICIT MODRM_REG
1 MEM0 MEM d R EXPLICIT MODRM_RM
2 REG1 REG d R EXPLICIT MODRM_REG
3 REG2 REG w W EXPLICIT MODRM_REG
4 MEM1 MEM d R EXPLICIT MODRM_RM
5 REG3 REG d R EXPLICIT MODRM_REG
6 REG4 REG w W EXPLICIT MODRM_REG
7 REG5 REG d R EXPLICIT MODRM_REG
8 REG6 REG d R EXPLICIT MODRM_REG
9 REG7 REG w W EXPLICIT MODRM_REG
10 REG8 REG d R EXPLICIT MODRM_REG
11 REG9 REG d R EXPLICIT MODRM_REG
12 REG10 REG w W EXPLICIT MODRM_REG
13 MEM2 MEM q R EXPLICIT MODRM_RM
14 REG11 REG q R EXPLICIT MODRM_REG
15 REG12 REG w W EXPLICIT MODRM_REG
16 REG13 REG q R EXPLICIT MODRM_REG
17 REG14 REG q R EXPLICIT MODRM_REG

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.