SHRD
REG0=GPRv_B():rcw:v REG1=GPRv_R():r:v REG2=XED_REG_CL:r:IMPL
x86_64 X86_LEGACY SHIFT APX_F_N3 source: xed
XED_SHRD_GPRv_GPRv_CL_APX_N3
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | AD |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| vex_l | 0 |
| requires_mode | long |
| attributes | APX_NF |
| exception_class | APX-EVEX-INT |
| cpl | 3 |
| raw_encoding | EVV 0xAD VNP MAP4 MOD[0b11] MOD=3 UBIT=1 REG[rrr] RM[nnn] ND=0 NF=1 VL128 mode64 NOEVSR ZEROING=0 EVAPX() |
Operands (3)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | v | R | EXPLICIT | MODRM_REG | |
| 1 | REG1 | REG | v | R | EXPLICIT | MODRM_REG | |
| 2 | REG2 | REG | (=CL) | R | IMPLICIT | MODRM_REG |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.