SHRD
MEM0:rcw:v REG0=GPRv_R():r REG1=XED_REG_CL:r:IMPL REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=XED_REG_CL:r:IMPL
x86_64 X86_LEGACY SHIFT I386 source: xed
XED_SHRD_X86_LEGACY_0F_AD_522637
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | AD 0F AD |
| opcode_map | 0F |
| mandatory_prefix | - |
| has_modrm | True |
| cpl | 3 |
| raw_encoding | 0x0F 0xAD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0F 0xAD MOD[0b11] MOD=3 REG[rrr] RM[nnn] |
Operands (6)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | MEM0 | MEM | v | R | EXPLICIT | MODRM_RM | |
| 1 | REG0 | REG | R | EXPLICIT | MODRM_REG | ||
| 2 | REG1 | REG | (=CL) | R | IMPLICIT | MODRM_REG | |
| 3 | REG2 | REG | R | EXPLICIT | MODRM_REG | ||
| 4 | REG3 | REG | R | EXPLICIT | MODRM_REG | ||
| 5 | REG4 | REG | (=CL) | R | IMPLICIT | MODRM_REG |
Flag effects (6)
CF = WRITE
PF = WRITE
AF = UNDEFINED
ZF = WRITE
SF = WRITE
OF = UNDEFINED
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.