SUB
BINARY APX_F x86_64
SUB is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category BINARY. This page lists its 52 encoding forms, distinguished by opcode bytes: 28, 29, 2A, 2B, 2C, 2D, 80, 81 and 2 more.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_SUB_GPR8_GPR8_28
REG0=GPR8_B():rw REG1=GPR8_R():r
XED_SUB_GPR8_GPR8_2A
REG0=GPR8_R():rw REG1=GPR8_B():r REG0=GPR8_R():rw MEM0:r:b
XED_SUB_GPR8i8_GPR8i8_APX
REG0=GPR8_B():rw:b:i8 REG1=GPR8_R():r:b:i8
XED_SUB_GPR8i8_GPR8i8_APX_N3
REG0=GPR8_B():rw:b:i8 REG1=GPR8_R():r:b:i8
XED_SUB_GPR8i8_GPR8i8_GPR8i8_APX_N3
REG0=GPR8_N():w:b:i8 REG1=GPR8_B():r:b:i8 REG2=GPR8_R():r:b:i8
XED_SUB_GPR8i8_GPR8i8_IMM8_APX_N3
REG0=GPR8_N():w:b:i8 REG1=GPR8_B():r:b:i8 IMM0:r:b:i8
XED_SUB_GPR8i8_GPR8i8_MEMi8_APX_N3
REG0=GPR8_N():w:b:i8 REG1=GPR8_R():r:b:i8 MEM0:r:b:i8
XED_SUB_GPR8i8_IMM8_APX
REG0=GPR8_B():rw:b:i8 IMM0:r:b:i8
XED_SUB_GPR8i8_IMM8_APX_N3
REG0=GPR8_B():rw:b:i8 IMM0:r:b:i8
XED_SUB_GPR8i8_MEMi8_APX
REG0=GPR8_R():rw:b:i8 MEM0:r:b:i8
XED_SUB_GPR8i8_MEMi8_APX_N3
REG0=GPR8_R():rw:b:i8 MEM0:r:b:i8
XED_SUB_GPR8i8_MEMi8_GPR8i8_APX_N3
REG0=GPR8_N():w:b:i8 MEM0:r:b:i8 REG1=GPR8_R():r:b:i8
XED_SUB_GPR8i8_MEMi8_IMM8_APX_N3
REG0=GPR8_N():w:b:i8 MEM0:r:b:i8 IMM0:r:b:i8
XED_SUB_GPR8_IMMb_80r5
REG0=GPR8_B():rw IMM0:r:b:i8
XED_SUB_GPR8_IMMb_82r5
REG0=GPR8_B():rw IMM0:r:b:i8
XED_SUB_GPRv_GPRv_29
REG0=GPRv_B():rw REG1=GPRv_R():r
XED_SUB_GPRv_GPRv_2B
REG0=GPRv_R():rw REG1=GPRv_B():r REG0=GPRv_R():rw MEM0:r:v
XED_SUB_GPRv_GPRv_APX
REG0=GPRv_B():rw:v REG1=GPRv_R():r:v
XED_SUB_GPRv_GPRv_APX_N3
REG0=GPRv_B():rw:v REG1=GPRv_R():r:v
XED_SUB_GPRv_GPRv_GPRv_APX_N3
REG0=GPRv_N():w:v REG1=GPRv_B():r:v REG2=GPRv_R():r:v
XED_SUB_GPRv_GPRv_IMM8_APX_N3
REG0=GPRv_N():w:v REG1=GPRv_B():r:v IMM0:r:b:i8
XED_SUB_GPRv_GPRv_IMMz_APX_N3
REG0=GPRv_N():w:v REG1=GPRv_B():r:v IMM0:r:z
XED_SUB_GPRv_GPRv_MEMv_APX_N3
REG0=GPRv_N():w:v REG1=GPRv_R():r:v MEM0:r:v
XED_SUB_GPRv_IMM8_APX
REG0=GPRv_B():rw:v IMM0:r:b:i8
XED_SUB_GPRv_IMM8_APX_N3
REG0=GPRv_B():rw:v IMM0:r:b:i8
XED_SUB_GPRv_IMMz_APX
REG0=GPRv_B():rw:v IMM0:r:z
XED_SUB_GPRv_IMMz_APX_N3
REG0=GPRv_B():rw:v IMM0:r:z
XED_SUB_GPRv_MEMv_APX
REG0=GPRv_R():rw:v MEM0:r:v
XED_SUB_GPRv_MEMv_APX_N3
REG0=GPRv_R():rw:v MEM0:r:v
XED_SUB_GPRv_MEMv_GPRv_APX_N3
REG0=GPRv_N():w:v MEM0:r:v REG1=GPRv_R():r:v
XED_SUB_GPRv_MEMv_IMM8_APX_N3
REG0=GPRv_N():w:v MEM0:r:v IMM0:r:b:i8
XED_SUB_GPRv_MEMv_IMMz_APX_N3
REG0=GPRv_N():w:v MEM0:r:v IMM0:r:z
XED_SUB_MEMb_IMMb_80r5
MEM0:rw:b IMM0:r:b:i8
XED_SUB_MEMb_IMMb_82r5
MEM0:rw:b IMM0:r:b:i8
XED_SUB_MEMi8_GPR8i8_APX
MEM0:rw:b:i8 REG0=GPR8_R():r:b:i8
XED_SUB_MEMi8_GPR8i8_APX_N3
MEM0:rw:b:i8 REG0=GPR8_R():r:b:i8
XED_SUB_MEMi8_IMM8_APX
MEM0:rw:b:i8 IMM0:r:b:i8
XED_SUB_MEMi8_IMM8_APX_N3
MEM0:rw:b:i8 IMM0:r:b:i8
XED_SUB_MEMv_GPRv_APX
MEM0:rw:v REG0=GPRv_R():r:v
XED_SUB_MEMv_GPRv_APX_N3
MEM0:rw:v REG0=GPRv_R():r:v
XED_SUB_MEMv_IMM8_APX
MEM0:rw:v IMM0:r:b:i8
XED_SUB_MEMv_IMM8_APX_N3
MEM0:rw:v IMM0:r:b:i8
XED_SUB_MEMv_IMMz_APX
MEM0:rw:v IMM0:r:z
XED_SUB_MEMv_IMMz_APX_N3
MEM0:rw:v IMM0:r:z
XED_SUB_X86_LEGACY_ONEBYTE_28_660894
MEM0:rw:b REG0=GPR8_R():r
XED_SUB_X86_LEGACY_ONEBYTE_29_363843
MEM0:rw:v REG0=GPRv_R():r
XED_SUB_X86_LEGACY_ONEBYTE_2C_630561
REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8
XED_SUB_X86_LEGACY_ONEBYTE_2D_342066
REG0=OrAX():rw:IMPL IMM0:r:z
XED_SUB_X86_LEGACY_ONEBYTE_81_400850
MEM0:rw:v IMM0:r:z
XED_SUB_X86_LEGACY_ONEBYTE_81_83647
REG0=GPRv_B():rw IMM0:r:z
XED_SUB_X86_LEGACY_ONEBYTE_83_372210
REG0=GPRv_B():rw IMM0:r:b:i8
XED_SUB_X86_LEGACY_ONEBYTE_83_881039
MEM0:rw:v IMM0:r:b:i8