VAESDECLAST
AES AVXAES x86_64
VAESDECLAST is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AES. This page lists its 9 encoding forms, distinguished by opcode byte: DF.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VAESDECLAST_X86_LEGACY_ONEBYTE_DF_205236
REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq
XED_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512
REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128
XED_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512
REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128
XED_VAESDECLAST_YMMu128_YMMu128_MEMu128
REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128
XED_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512
REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128
XED_VAESDECLAST_YMMu128_YMMu128_YMMu128
REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128
XED_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512
REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128
XED_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512
REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128
XED_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512
REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128